Generally, semiconductor devices are manufactured by repeatedly performing various processes such as a film forming process or a pattern etching process on a semiconductor wafer. To meet a demand for a higher degree of integration and miniaturization of semiconductor devices, a line width or a hole diameter become gradually reduced. Since it is required to reduce an electrical resistance due to a scaling-down of various dimensions, inexpensive copper having a small electrical resistance tends to be used as a wiring material or a material to be filled in a recess such as a trench or a hole or the like (see, Japanese Patent Laid-open Publication No. 2004-107747). When copper is used as the wiring material or the filling material, generally, a tantalum metal (Ta) film or a tantalum nitride (TaN) film is used as a barrier layer in consideration of its barrier property against copper diffusion to an underlying layer thereof.
In order to fill a recess with the copper, a thin seed film such as a copper film is formed on the entire surface of the wafer including the entire wall of the recess by a plasma sputtering apparatus. Then, the entire surface of the wafer is plated with copper so as to completely fill the recess. Thereafter, remnants of a copper thin film on the surface of the wafer are polished and removed by means of a CMP (Chemical Mechanical Polishing).
Such a process will be explained with reference to FIG. 12. FIG. 12 is a process diagram showing a conventional filling process for a recess of a semiconductor wafer. A recess 2 corresponding to a via hole, a through hole, or a groove (trench) of a single damascene structure, a dual damascene structure, or a three-dimensional package structure is formed on a surface of an insulating layer 1 formed on a semiconductor wafer W. Here, the insulating layer 1 serves as an interlayer insulating film made of, for example, a SiO2 film. Further, an underlying wiring layer 3 made of, for example, copper is exposed to a bottom of the recess 2.
To be specific, the recess 2 includes a groove (trench) 2A having a narrow and long recess shape as a cross sectional shape and a hole 2B formed at a part of a bottom of the groove 2A. This hole 2B becomes a via hole or a through hole. The wiring layer 3 is exposed to a bottom of the hole 2B, and is electrically connected to the underlying wiring layer or an element such as a transistor. Illustration of the underlying wiring layer or the element such as the transistor is omitted. The recess 2 has a very small width or inner diameter such as about 120 nm in order to meet a scaling-down requirement of the design rule. An aspect ratio thereof is required to be, for example, about 2 to about 4. Illustration of a diffusion barrier layer and an etching stop film is omitted, and a simple shape is shown in FIG. 12.
On a surface of this semiconductor wafer W including an inner surface of the recess 2, a barrier layer 4 including, for example, a TaN film and a Ta film in a layered structure is substantially uniformly pre-formed by a plasma sputtering apparatus (see FIG. 12(A)). Then, a seed film 6, made of a thin copper film, as a metal film is formed over the entire surface of the wafer including the inner surface of the recess 2 by the plasma sputtering apparatus (see FIG. 12(B)). By performing a copper plating process on the surface of the wafer, the inside of the recess 2 is filled with a metal film 8 such as a copper film (see FIG. 12 (C)). Thereafter, remnants of the metal film 8, the seed film 6 and the barrier layer 4 on the surface of the wafer are polished and removed by means of the CMP or the like.
In order to increase reliability of the barrier layer, various developments have been made. Particularly, attention is given to a self-forming barrier layer using a Mn film or a CuMn alloy film instead of using the Ta film or the TaN film (see Japanese Patent Laid-open Publication No. 2005-277390). The Mn film or the CuMn alloy film is formed by means of a sputtering method. Further, the Mn film or the CuMn alloy film itself can serve as a seed film. Thus, a Cu plating layer can be directly formed thereon. Further, by performing an annealing process after the plating, the Mn film or the CuMn alloy film reacts with a SiO2 layer as an underlying insulating film by self-alignment. As a result, a MnSixOy film (x, y: a positive number) or a manganese oxide (MnOx) film (x: a positive number) is formed as a barrier layer. The MnSixOy film or the manganese oxide (MnOx) film is formed at a boundary between the SiO2 layer and the Mn film or between the SiO2 layer and the CuMn alloy film. Further, the manganese oxide (MnOx) film is formed by a reaction between Mn and oxygen in the SiO2 layer. As a result, the number of processes can be reduced. The manganese oxide includes MnO, Mn3O4, Mn2O3, and MnO2 depending on a valency of Mn. In the present disclosure, these oxides are generally referred to as “MnOx”. Further, there has been discussed that a MnSixOy film or a MnOx film is formed by means of a CVD method capable of forming a film having a fine line width or a fine hole diameter with a good step coverage as compared with the sputtering method (see Japanese Patent Laid-open Publication No. 2008-013848).
However, recently, to meet a demand for a higher speed of semiconductor devices, the interlayer insulating film needs to have a lower specific permittivity (relative permittivity). By this demand, there has been considered to use a low-k film as a material of an interlayer insulating film, instead of a silicon oxide film made of TEOS. The low-k film is made of, e.g., SiOC and SiCOH containing an organic group such as a methyl group, and has a lower specific permittivity. Herein, the silicon oxide film made of the TEOS has a specific permittivity of about 4.1, whereas the low-k film made of SiOC has a specific permittivity of about 3.0. However, if the low-k film is used as the interlayer insulating film, a MnOx film is hardly formed thereon even if a process for forming a Mn-containing film is performed by a CVD on a surface of the interlayer insulating film, which has a low specific permittivity, including an exposed surface of the recess. Therefore, a barrier layer cannot be formed thereon.